Analog to digital converters, such as successive approximation routine, SAR, converters often include a switched capacitor charge redistribution digital to analog converter having a plurality of weighted capacitors therein. As is known to the person skilled in the art, a successive approximation conversion can be performed by successively performing bit trials from a most significant bit to a least significant bit, and on the basis of comparing the output voltage from the switched capacitor digital to analog converter with a reference, deciding whether the currently trialled bit should be kept or reset, so as to eventually arrive at a bit pattern that best represents the analog input that is being converted by the analog to digital converter.
As part of this trial, “bottom plates” of the capacitors (as shown in FIG. 1) within the charge redistribution digital to analog converter within the SAR analog to digital converter are successively switched between a first voltage reference Vref1 and a second voltage reference Vref2. Typically Vref1 is held at a positive voltage by a reference circuit and Vref2 is a local ground, or Vref1 and Vref2 may be placed either side of a mid-point, such
      Vdd    2    .
The voltage Vref1 is typically provided by an external voltage reference, such as a band gap reference, which drives a reference buffer. The output from the reference buffer is used to charge a reference capacitor which is generally large, having a value of 10 μF or so which has to be physically placed near the reference input pins of an integrated circuit incorporating the charge redistribution analog to digital converter.
The transfer of the reference voltage from the external capacitor to the on chip charge redistribution digital to analog converter, DAC, that is implemented within an analog to digital converter, ADC, occurs via tracks on a printed circuit board, package pins and often via bond wires connecting the package pins to the integrated circuit itself. Each of these components exhibits an inductance.
Operation of the charge redistribution ADC having a capacitor array DAC causes a varying capacitive load to be connected to the reference circuit. It is for this reason that the storage capacitor and reference voltage buffer are provided, which together provide the charge to maintain the reference voltage across the DAC at a fixed value. However use of the reference voltage buffer is expensive in terms of current consumption and itself can introduce a source of inaccuracy due to offset and noise.